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| author |  Nick Brassel <nick@tzarc.org> | 2019-06-02 09:04:09 +1000 |
|---|---|---|
| committer |  Drashna Jaelre <drashna@live.com> | 2019-06-01 16:04:09 -0700 |
| commit | 155be34a1d2b782a73318cc507315b33cc86cc49 (patch) | |
| tree | 842b3fa9e4881d18932a0e01666dec5a8144d3b2 /drivers/arm/i2c_master.h | |
| parent | 4f788c2ae90583f64e0cec6545a3da75a5aff0f8 (diff) | |
| download | qmk_firmware-155be34a1d2b782a73318cc507315b33cc86cc49.tar.gz | |
Parameterise STM32 I2C pin modes and timing parameters. (#5671)
I2C timing parameters were seemingly set up for an STM32F303 target MCU, at a specific clock speed. This commit allows specifying the timing parameters via config.h, allowing other STM32 MCUs to be targeted, potentially at different clock frequencies.
Alternate function modes for the I2C pins are now also configurable, allowing for remapping to other pins.
Diffstat (limited to 'drivers/arm/i2c_master.h')
| -rw-r--r-- | drivers/arm/i2c_master.h | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h index a15f1702d..1bb74c800 100644 --- a/drivers/arm/i2c_master.h +++ b/drivers/arm/i2c_master.h @@ -26,9 +26,19 @@ #include "ch.h" #include <hal.h> -#ifndef I2C1_BANK - #define I2C1_BANK GPIOB +#ifdef I2C1_BANK + #define I2C1_SCL_BANK I2C1_BANK + #define I2C1_SDA_BANK I2C1_BANK #endif + +#ifndef I2C1_SCL_BANK + #define I2C1_SCL_BANK GPIOB +#endif + +#ifndef I2C1_SDA_BANK + #define I2C1_SDA_BANK GPIOB +#endif + #ifndef I2C1_SCL #define I2C1_SCL 6 #endif @@ -36,6 +46,32 @@ #define I2C1_SDA 7 #endif +// The default PAL alternate modes are used to signal that the pins are used for I2C +#ifndef I2C1_SCL_PAL_MODE + #define I2C1_SCL_PAL_MODE 4 +#endif +#ifndef I2C1_SDA_PAL_MODE + #define I2C1_SDA_PAL_MODE 4 +#endif + +// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock +// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html +#ifndef I2C1_TIMINGR_PRESC + #define I2C1_TIMINGR_PRESC 15U +#endif +#ifndef I2C1_TIMINGR_SCLDEL + #define I2C1_TIMINGR_SCLDEL 4U +#endif +#ifndef I2C1_TIMINGR_SDADEL + #define I2C1_TIMINGR_SDADEL 2U +#endif +#ifndef I2C1_TIMINGR_SCLH + #define I2C1_TIMINGR_SCLH 15U +#endif +#ifndef I2C1_TIMINGR_SCLL + #define I2C1_TIMINGR_SCLL 21U +#endif + #ifndef I2C_DRIVER #define I2C_DRIVER I2CD1 #endif |