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| author |  yulei <yuleiz@gmail.com> | 2020-03-07 21:19:06 +0800 |
|---|---|---|
| committer |  GitHub <noreply@github.com> | 2020-03-07 13:19:06 +0000 |
| commit | e0d15e6182a331ed27535f81539f2d7243d02bc0 (patch) | |
| tree | a56d2c479654151aaf3bedd253db705a81c54b9b /keyboards/matrix/noah/mcuconf.h | |
| parent | 3a303bd2aec57fd2d4d0f6d3e5583d746367d6e1 (diff) | |
| download | qmk_firmware-e0d15e6182a331ed27535f81539f2d7243d02bc0.tar.gz | |
Diffstat (limited to 'keyboards/matrix/noah/mcuconf.h')
| -rw-r--r-- | keyboards/matrix/noah/mcuconf.h | 61 |
1 files changed, 23 insertions, 38 deletions
diff --git a/keyboards/matrix/noah/mcuconf.h b/keyboards/matrix/noah/mcuconf.h index 8405d61e1..54a1f2661 100644 --- a/keyboards/matrix/noah/mcuconf.h +++ b/keyboards/matrix/noah/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -57,14 +57,32 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 2 +#define STM32_PLLI2SR_VALUE 5 #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE /* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* * ADC driver system settings. */ #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 @@ -75,22 +93,6 @@ #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* - * EXT driver system settings. - */ -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 - -/* * GPT driver system settings. */ #define STM32_GPT_USE_TIM1 FALSE @@ -164,9 +166,9 @@ * PWM driver system settings. */ #define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM9 FALSE @@ -182,11 +184,9 @@ */ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_USART6_PRIORITY 12 /* @@ -195,28 +195,18 @@ #define STM32_SPI_USE_SPI1 TRUE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI5_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -230,23 +220,18 @@ */ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_USART6 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |